Why determinism matters more than throughput
A neural-interface stack that misses its 800 µs frame deadline doesn't just drop a sample — it loses a closed-loop guarantee that downstream BCI applications rely on for stimulation timing. ENI 0.6's redesigned pipeline holds that frame deadline at p99.99 across 1,024 simultaneously sampled channels.
The hardest part wasn't the math. The math is well-understood: bandpass, common-average referencing, threshold-based detection, template matching. The hardest part was scheduling four cooperating cores so that filter, sort, decode, and feedback never compete for the same memory bank.
The frame
An 800 µs ENI frame at 25 kHz sample rate carries 20 samples per channel. The pipeline walks them through five stages:
- DMA gather from the front-end ADC (≤ 80 µs)
- Bandpass + CAR filtering on Core 0 (≤ 220 µs)
- Threshold detection + spike alignment on Core 1 (≤ 180 µs)
- Template-matched sorting on Core 2 (≤ 200 µs)
- Decoder + closed-loop output on Core 3 (≤ 100 µs slack)
The slack on Core 3 absorbs jitter. At p99.99 we measured 642 µs total — a comfortable 158 µs of headroom.
Memory bank scheduling
The platform we benchmark on (a 4-core Cortex-A78 with eight independent SRAM banks) was the only place this was easy. On targets with shared L2, the pipeline drops to 16 channels per core block. ENI's scheduler emits target-specific tile sizes at build time — see the eni-tile-search tool that ships with eos-platform 1.0.
Open data
All the benchmark traces (4.2 GB) are mirrored on the foundation's research bucket. See the research page for access details.
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