Changelog
A record of all notable changes across the EmbeddedOS product family. Follows Keep a Changelog conventions and Semantic Versioning.
Latest
v0.1.0 — 2025-Q2
EoS
Added
- Preemptive priority-based real-time scheduler with time-slicing
- SMP (Symmetric Multi-Processing) and AMP (Asymmetric Multi-Processing) multicore modes
- 33-peripheral Hardware Abstraction Layer (HAL): UART, SPI, I²C, GPIO, CAN, USB, ETH, ADC, PWM, Timer, DMA, RTC, Crypto, and more
- 41 Board Support Package (BSP) product profiles
- Capability-based security model with unforgeable process tokens
- Hot-pluggable driver framework
- POSIX-compatible system call interface
- C11 kernel implementation
eBootloader
Added
- ECDSA-256 (NIST P-256) firmware signature verification
- SHA-256 hash chain for multi-stage boot integrity
- Anti-rollback counter in OTP/eFuse with configurable policy
- AES-256-GCM encrypted firmware image support
- ARM TrustZone secure world handoff
- Dual-bank A/B OTA update with atomic swap and automatic rollback
- JTAG/SWD debug lock-out in production mode
- Support for ARM Cortex-M/A/R, RISC-V RV32/RV64, x86 (UEFI), MIPS, ARC, Xtensa
EAI
Added
- INT4, INT8, FP16, and FP32 quantized inference runtime
- ARM Helium MVE acceleration for Cortex-M55 and M85
- TFLite Micro, ONNX Runtime, PyTorch Mobile, CMSIS-NN, and GGUF model format support
- Post-training quantization (PTQ) and quantization-aware training (QAT) toolchain
- 11.2 tok/s LLM inference on Cortex-M85 @ 480 MHz (INT4)
- 200+ operator coverage including Transformer attention and depthwise separable convolutions
eBuild
Added
- CMake 3.25+ with Ninja generator for parallel builds
- Support for GCC 13+, Clang/LLVM 17+, ARM Compiler 6, IAR EWARM, RISC-V GCC, Xtensa GCC, MinGW-w64, MSVC 2022
- 41 pre-configured target profile presets
- Automatic SDK generation with headers, libraries, and CMake package config
- GitHub Actions, GitLab CI, Jenkins, and Buildkite native CI/CD integration
- Integrated clang-tidy, cppcheck, and MISRA-C 2012 static analysis
- GCOV/LCOV code coverage reports
Upcoming
v0.2.0 — Planned Q4 2025
ENI
Added
- 1,024-channel neural signal acquisition at 30 kS/s per channel
- 24-bit ADC array with configurable bandpass filtering
- Real-time spike sorting with 99.2% accuracy
- BCI protocol stack with USB 3.0 and LVDS output
- EoSim HIL integration for closed-loop BCI simulation
EIPC
Added
- Zero-copy shared memory channels with page-mapped regions
- Lock-free inter-core queues for SMP systems
- Capability token delegation and revocation
- Runtime deadlock detection with cycle detection (debug builds)
- Priority inheritance on mutexes
EoSim
Added
- Sub-microsecond HIL bridge latency
- 16-peripheral simulation (UART, SPI, I²C, GPIO, CAN, USB, ETH, ADC, PWM, Timer, DMA, RTC, Flash, SDIO, QSPI, LCD)
- Fault injection framework: bit-flip, peripheral timeout, power-loss
- EoStudio one-click launch integration
- Branch coverage in instrumented builds
eDB
Added
- ACID transactions with Write-Ahead Logging (WAL) and MVCC
- AES-256-XTS per-page encryption with HKDF-SHA256 key derivation
- B-Tree and Hash index types
- SQL subset query language with JSON Path support
- NOR Flash, NAND Flash, SD/eMMC, QSPI Flash, and SRAM backends
- 64 KB minimum RAM configuration