EmbeddedOS HARDWARE · ORIGINAL BOARD DESIGNS

EmbeddedOS development boards

Original development boards designed by Kartikeydheer Srivastava for EmbeddedOS: complete KiCad designs, each with the check results its build recorded.

Every board here is designed and checked in KiCad; not yet manufactured or bench-tested. None has been built or powered.

Licence: not open source

  • These boards are Copyright (c) 2026 Kartikeydheer Srivastava, all rights reserved, and not open source. They are not under the MIT licence that covers EmbeddedOS software.
  • Anyone may view them. Copying, modifying, manufacturing or selling needs written permission from Kartikeydheer Srivastava, which may be given for a fee. Contact kartikeydheer@gmail.com.
  • EmbeddedOS (EoS) Research Foundation has a limited, revocable permission to use them.
  • Third-party material on a board keeps its own licence; each board lists its own below. The full terms are in the LICENSE.txt file in each board's folder.

From circuit to board

The schematic describes what connects. The PCB file places those parts and draws the copper connections. Each board below includes both files, its recorded checks and views rendered from the PCB.

  1. 01

    Define the circuit

    Component datasheets set pin assignments, supply limits and component values. Published dimensions and pinouts guide the connectors. Each board identifies its sources and any third-party material.

  2. 02

    Place and route

    Parts receive physical footprints. Copper tracks, vias and planes connect the schematic’s nets, with critical signals and supply connections laid first.

  3. 03

    Check the CAD

    KiCad checks the schematic, physical clearances, missing connections and agreement between the two files. The results below belong to a specific saved revision.

  4. 04

    Inspect the views

    Perspective, top, bottom and rotating views come from that board’s CAD. Missing component models can leave empty areas in a render; the PCB file still records the fitted footprints.

What the checks mean

One command generates each board's schematic, layout, routing and fabrication files and runs KiCad's checks. The counts on this page are copied from the report that command wrote. They show the design is consistent; they cannot show that a manufactured board works.

ERC
KiCad's electrical rules check on the schematic: outputs driven together, inputs left floating, power pins with no source.
DRC errors
KiCad's design rules check on the layout: clearances, track widths, drill sizes and copper too close to the board edge.
Unconnected items
Connections the schematic asks for that the copper on the board does not yet make.
Schematic parity
Differences between the schematic and the board: a part or a net present in one and missing from the other.
DRC warnings
Findings KiCad reports as warnings rather than errors. Each board below says what its warnings are.
Perspective render of the EoS Learn RP2350 from its KiCad 3D model: the RP2350A at the centre, a 20-pin header down each side and the USB-C connector on one edge
Perspective
Top side of the EoS Learn RP2350, rendered from its KiCad 3D model
Top
Bottom side of the EoS Learn RP2350, rendered from its KiCad 3D model
Bottom

Renders and animation © 2026 Kartikeydheer Srivastava. All rights reserved.

EoS Learn RP2350

A teaching board for the RP2350A, built around Raspberry Pi's own core layout, reproduced to the nanometre.

Status: designed and checked in KiCad; not yet manufactured or bench-tested.

Main chip
Raspberry Pi RP2350A
Size
52.6 × 51.6 mm
Layers
4 (signal, GND plane, 3.3 V plane, signal; 1.6 mm)

Checks, as recorded

ERC violations
0
DRC errors
0
Unconnected
0
Schematic parity
0
DRC warnings
4

The 4 warnings: Two short 3.3 V track ends in Raspberry Pi's unchanged copper, and two USB-C silkscreen lines clipped at the board edge, where the connector is meant to sit.

From build-report.json and drc.json in the board's folder, KiCad 10.0.6, commit 28ec996.

Key features, what is not done yet, and third-party material

Key features

  • RP2350A with a 12 MHz crystal and 128 Mbit QSPI flash (W25Q128JV)
  • Raspberry Pi's RP2350A Minimal Design R4 core layout, kept unchanged: the parts' positions and 124 tracks, 25 vias and 7 zones are checked against it to KiCad's 1 nm resolution
  • USB-C 5 V sink with USBLC6-2SC6 ESD protection
  • 500 mA polyfuse and a Schottky diode, so 5 V fed into the header never reaches the USB host, then an AP7361C 3.3 V regulator
  • All 30 GPIOs on two 1×20, 2.54 mm headers, in pin order
  • Qwiic (I2C0 on GPIO4/5) and a Raspberry Pi Debug Probe SWD connector
  • BOOTSEL and RUN buttons, a power LED and a user LED on GPIO25

Not done yet

  • This board has not been manufactured, powered or tested on the bench.
  • No signal-integrity simulation of USB or QSPI. The QSPI routing is Raspberry Pi's own.

Third-party material, under its own licence

  • RP2350A core layout: Raspberry Pi RP2350A Minimal Design R4, Copyright (c) 2026 Raspberry Pi Ltd, MIT licence
  • Footprints, symbols and 3D models from KiCad's libraries: CC BY-SA 4.0, with the KiCad libraries' exception for designs that use them and files generated from those designs
Schematic (.kicad_sch) for EoS Learn RP2350PCB layout (.kicad_pcb) for EoS Learn RP2350

Native KiCad files from commit 28ec996, for viewing under this board’s full licence. Keep the licence with any permitted copies. The GitHub folder includes the project settings and supporting files.

EoS Learn RP2350 files on GitHub All boards
Perspective render of the EoS ESP32 DevKit from its KiCad 3D model: the ESP32-WROOM-32E module at one end with its antenna past the edge, the EN and BOOT buttons, and a 19-pin header down each side
Perspective
Top side of the EoS ESP32 DevKit, rendered from its KiCad 3D model
Top
Bottom side of the EoS ESP32 DevKit, rendered from its KiCad 3D model
Bottom

Renders and animation © 2026 Kartikeydheer Srivastava. All rights reserved.

EoS ESP32 DevKit

A breadboard development board for the Espressif ESP32-WROOM-32E module: the same job as Espressif's ESP32-DevKitC V4, in an original design.

Status: designed and checked in KiCad; not yet manufactured or bench-tested.

Main chip
Espressif ESP32 (ESP32-WROOM-32E-N4 module)
Size
27.94 × 48.76 mm
Layers
2 (ground poured on both sides; 1.6 mm)

Checks, as recorded

ERC violations
0
DRC errors
0
Unconnected
0
Schematic parity
0
DRC warnings
8

The 8 warnings: Silkscreen past the board edge: the header rows and the USB-C connector sit at the edge, and the module's outline runs over its antenna overhang.

From build-report.json and drc.json in the board's folder, KiCad 10.0.6, commit 28ec996.

Key features, what is not done yet, and third-party material

Key features

  • ESP32-WROOM-32E-N4 module (4 MB flash, no PSRAM), its whole antenna area overhanging the top edge so the antenna keep-out lies off the board
  • USB-C 5 V sink with SP0503BAHTG ESD protection, a 500 mA polyfuse and a Schottky diode, so 5 V fed into the 5V pin cannot reach the USB host
  • CP2102N USB-UART bridge with esptool's two-transistor automatic reset into the bootloader
  • AP7361C-33 1 A 3.3 V regulator
  • EN and BOOT buttons, a power LED and a user LED on IO4
  • Every usable GPIO on two 1×19, 2.54 mm headers, on the DevKitC V4's header grid and in its pin order, with the JTAG pins there for an external adapter

Not done yet

  • This board has not been manufactured, powered or tested on the bench.
  • Nothing has been measured: not the antenna on this base board, the regulator's temperature, the Schottky's leakage or the auto-reset timing with esptool.

Third-party material, under its own licence

  • Header grid, 27.94 mm board width and J2/J3 pin order from Espressif's ESP32-DevKitC V4 user guide and dimension drawing, used as positions and pin names only
  • Footprints, symbols and 3D models from KiCad's libraries: CC BY-SA 4.0, with the KiCad libraries' exception for designs that use them and files generated from those designs
Schematic (.kicad_sch) for EoS ESP32 DevKitPCB layout (.kicad_pcb) for EoS ESP32 DevKit

Native KiCad files from commit 28ec996, for viewing under this board’s full licence. Keep the licence with any permitted copies. The GitHub folder includes the project settings and supporting files.

EoS ESP32 DevKit files on GitHub All boards
Perspective render of the EoS Probe S3 from its KiCad 3D model: the ESP32-S3 module on one end with its antenna past the board edge, six level shifters in the middle and the USB-C connector on the other end
Perspective
Top side of the EoS Probe S3, rendered from its KiCad 3D model
Top
Bottom side of the EoS Probe S3, rendered from its KiCad 3D model
Bottom

Renders and animation © 2026 Kartikeydheer Srivastava. All rights reserved.

EoS Probe S3

An ESP32-S3 debug probe for Arm SWD/JTAG targets and their UART, working at the target's own I/O voltage from 1.65 to 5.5 V.

Status: designed and checked in KiCad; not yet manufactured or bench-tested.

Main chip
Espressif ESP32-S3 (ESP32-S3-WROOM-1-N8R2 module)
Size
62 × 30 mm
Layers
2 (ground poured on both sides; 1.6 mm)

Checks, as recorded

ERC violations
0
DRC errors
0
Unconnected
0
Schematic parity
0
DRC warnings
4

The 4 warnings: Silkscreen past the board edge: the module's outline over its antenna, and the USB-C connector, which is meant to sit on the edge.

From build-report.json and drc.json in the board's folder, KiCad 10.0.6, commit 28ec996.

Key features, what is not done yet, and third-party material

Key features

  • ESP32-S3-WROOM-1-N8R2 module, its antenna past the board edge so Espressif's keep-out falls off the board
  • One SN74LVC1T45 level shifter per line, its target side powered from VTref, so an unpowered target is never driven
  • Arm 10-pin Cortex Debug header (1.27 mm) for SWD/JTAG with SWO and an open-drain nRESET
  • UART header (1×4, 2.54 mm)
  • VTref sensed by the ESP32-S3's ADC through a 100 kΩ / 100 kΩ divider
  • USB-C 5 V sink with USBLC6-2SC6 ESD protection, a 500 mA polyfuse and a 1 A AP7361C-33 regulator
  • Reset and boot buttons, status and activity LEDs

Not done yet

  • This board has not been manufactured, powered or tested on the bench.
  • No firmware: the pin assignment is meant for CMSIS-DAP probe firmware on the ESP32-S3, but none has been ported or run on this board.

Third-party material, under its own licence

  • Footprints, symbols and 3D models from KiCad's libraries: CC BY-SA 4.0, with the KiCad libraries' exception for designs that use them and files generated from those designs
Schematic (.kicad_sch) for EoS Probe S3PCB layout (.kicad_pcb) for EoS Probe S3

Native KiCad files from commit 28ec996, for viewing under this board’s full licence. Keep the licence with any permitted copies. The GitHub folder includes the project settings and supporting files.

EoS Probe S3 files on GitHub All boards
Perspective render of the EoS Sense Cape from its KiCad 3D model: two 2×18 sockets for PocketBeagle, with the sensors, two buttons and the Qwiic connector below them
Perspective
Top side of the EoS Sense Cape, rendered from its KiCad 3D model
Top
Bottom side of the EoS Sense Cape, rendered from its KiCad 3D model
Bottom

Renders and animation © 2026 Kartikeydheer Srivastava. All rights reserved.

EoS Sense Cape

A sensor cape for BeagleBoard.org PocketBeagle, its fit checked pin for pin against PocketBeagle's own board file.

Status: designed and checked in KiCad; not yet manufactured or bench-tested.

Main chip
Bosch BME280, ST LIS3DH and Broadcom APDS-9306 sensors; PocketBeagle is the host
Size
55 × 60 mm
Layers
2 (ground poured on both sides; 1.6 mm)

Checks, as recorded

ERC violations
0
DRC errors
0
Unconnected
0
Schematic parity
0
DRC warnings
0

From build-report.json and drc.json in the board's folder, KiCad 10.0.6, commit 28ec996.

Key features, what is not done yet, and third-party material

Key features

  • BME280 temperature, humidity and pressure sensor on I2C1 at 0x76
  • LIS3DH accelerometer on I2C1 at 0x18, its INT1 on P2.03
  • APDS-9306-065 ambient light sensor on I2C1 at 0x52
  • 24LC256 EEPROM on I2C2 at 0x57 for the cape's identity
  • 10 kΩ NTC thermistor on AIN5 and a trimmer on AIN6, kept under the processor's 1.8 V limit by PocketBeagle's own dividers
  • 4.7 kΩ pull-ups on I2C1 and I2C2, which PocketBeagle does not have
  • Two buttons, two PWM LEDs and a Qwiic / STEMMA QT connector
  • All 72 socket pads checked against PocketBeagle's header pins at KiCad's 1 nm resolution

Not done yet

  • This board has not been manufactured, powered or tested on the bench.

Third-party material, under its own licence

  • PocketBeagle outline and P1/P2 header positions from BeagleBoard.org PocketBeagle, CC BY 4.0, used unchanged as positions only
  • Footprints, symbols and 3D models from KiCad's libraries: CC BY-SA 4.0, with the KiCad libraries' exception for designs that use them and files generated from those designs
Schematic (.kicad_sch) for EoS Sense CapePCB layout (.kicad_pcb) for EoS Sense Cape

Native KiCad files from commit 28ec996, for viewing under this board’s full licence. Keep the licence with any permitted copies. The GitHub folder includes the project settings and supporting files.

EoS Sense Cape files on GitHub All boards
Perspective render of the EoS Motion Wing from its KiCad 3D model: the Feather header rows along both long edges, the two sensors between them and the address and interrupt solder jumpers
Perspective
Top side of the EoS Motion Wing, rendered from its KiCad 3D model
Top
Bottom side of the EoS Motion Wing, rendered from its KiCad 3D model
Bottom

Renders and animation © 2026 Kartikeydheer Srivastava. All rights reserved.

EoS Motion Wing

An accelerometer and temperature FeatherWing: the same job as Adafruit's ADXL343 + ADT7410 Sensor FeatherWing, in an original design.

Status: designed and checked in KiCad; not yet manufactured or bench-tested.

Main chip
Analog Devices ADXL343 accelerometer and ADT7410 temperature sensor; a Feather is the host
Size
50.8 × 22.86 mm
Layers
2 (ground poured on both sides; 1.6 mm)

Checks, as recorded

ERC violations
0
DRC errors
0
Unconnected
0
Schematic parity
0
DRC warnings
5

The 5 warnings: The header outlines on the back silkscreen sit near the board edge, where the Feather Specification puts the header rows, 0.05 in from the edge.

From build-report.json and drc.json in the board's folder, KiCad 10.0.6, commit 28ec996.

Key features, what is not done yet, and third-party material

Key features

  • ADXL343 3-axis accelerometer on the Feather's I2C bus at 0x53, or 0x1D with its address jumper moved
  • ADT7410 16-bit temperature sensor on the same bus at 0x48, with 0x49 to 0x4B set by jumpers
  • Both sensors run from the Feather's 3V pin and draw well under 1 mA
  • 10 kΩ I2C pull-ups through a solder jumper, to cut when the Feather or another wing already pulls the bus up
  • The ADXL343's INT1 and INT2 and the ADT7410's INT and CT reach D5, D6, D10 and D11 through solder jumpers, open as delivered
  • FeatherWing outline, corner holes and header positions from Adafruit's Feather Specification, with male 1×16 and 1×12 headers on the back

Not done yet

  • This board has not been manufactured, powered or tested on the bench.
  • The ADXL343 values come from its data sheet Rev. 0; they have not been checked against the current Rev. A.
  • How the accelerometer behaves on a Feather stack, away from a hard mounting point, has not been checked.
  • The I2C pull-up limits are calculated, not measured, and no firmware or driver has been run against the board.

Third-party material, under its own licence

  • FeatherWing outline, corner holes, header positions and pin order from Adafruit's Feather Specification, used as dimensions only
  • Schematic symbols in hardware/symbols (EoS_Sensors.kicad_sym), written by the repository's generator: MIT licence
  • Footprints, symbols and 3D models from KiCad's libraries: CC BY-SA 4.0, with the KiCad libraries' exception for designs that use them and files generated from those designs
Schematic (.kicad_sch) for EoS Motion WingPCB layout (.kicad_pcb) for EoS Motion Wing

Native KiCad files from commit 28ec996, for viewing under this board’s full licence. Keep the licence with any permitted copies. The GitHub folder includes the project settings and supporting files.

EoS Motion Wing files on GitHub All boards
Perspective render of the EoS CM4 Base from its KiCad 3D model: the footprints of the two 100-pin module connectors, the MagJack's pads and the 40-pin GPIO header along one edge
Perspective
Top side of the EoS CM4 Base, rendered from its KiCad 3D model
Top
Bottom side of the EoS CM4 Base, rendered from its KiCad 3D model
Bottom

Renders and animation © 2026 Kartikeydheer Srivastava. All rights reserved.

EoS CM4 Base

A carrier board for the Raspberry Pi Compute Module 4: the same job as Raspberry Pi's CM4 IO Board, in an original design built on EoS CM5 Base's layout.

Status: designed and checked in KiCad; not yet manufactured or bench-tested.

Main chip
Raspberry Pi Compute Module 4, on two 100-pin connectors
Size
90 × 80 mm
Layers
4 (signal, GND plane, 5 V plane, signal; 1.6 mm)

Checks, as recorded

ERC violations
0
DRC errors
0
Unconnected
0
Schematic parity
0
DRC warnings
4

The 4 warnings: Silkscreen of the USB-C connector (J3) and the RJ45 MagJack (J5) past the board edge, where edge connectors belong.

From build-report.json and drc.json in the board's folder, KiCad 10.0.6, commit 28ec996.

Key features, what is not done yet, and third-party material

Key features

  • Two Hirose DF40C-100DS-0.4V 100-pin connectors for 1.5 mm stacking: all 200 pads, the four holes and every ground, 5 V, 3.3 V and GPIO pin's net checked at KiCad's 1 nm resolution, and the HDMI, camera, display, PCIe, 1.8 V and reserved pins checked to stay unconnected
  • USB-C power in, for a 5 V / 3 A supply, with 5.1 kΩ on CC1 and CC2
  • The CM4's one USB 2.0 port on two connectors: a jumper and a TI TS3USB30E switch send it to USB-C for rpiboot flashing and gadget mode, or to a USB-A host port whose 5 V comes through a TPS2051C
  • Gigabit Ethernet through a TRXCOM TRJG0926HENL MagJack, with TPD4EUSB30 ESD protection
  • microSD for CM4 Lite, powered through an RT9742GGJ5 switch
  • Standard 40-pin Raspberry Pi GPIO header at 3.3 V
  • Reset button through 220 Ω, a buffered power LED, an activity LED, a fan connector, and nRPIBOOT, EEPROM write-protect and USB host-mode jumpers
  • No copper on any layer under the module's PCB antenna: the 8 × 15 mm cut-out the CM4 datasheet calls ideal, checked by a test

Not done yet

  • This board has not been manufactured, powered or tested on the bench.
  • No signal-integrity simulation: the CM4 datasheet asks for 90 Ω differential pairs matched to 0.15 mm, and the generator matches no lengths, so the pairs are short but not matched.
  • The USB switch's effect on the USB eye has not been measured.
  • HDMI, PCIe and the camera and display (MIPI CSI and DSI) interfaces are left off on purpose, and there is no RTC coin cell or fan speed control.

Third-party material, under its own licence

  • CM4 pinout from the Raspberry Pi Compute Module 4 datasheet, section 4 (facts only)
  • Connector and mounting-hole positions from the CM5 footprint in Raspberry Pi's CM5 IO Board files, which Figure 4 of the CM4 and CM5 datasheets shows the CM4 shares (facts only)
  • Schematic symbols in hardware/symbols (EoS_Connectors.kicad_sym, EoS_Parts.kicad_sym), written by the repository's generator: MIT licence
  • Footprints, symbols and 3D models from KiCad's libraries: CC BY-SA 4.0, with the KiCad libraries' exception for designs that use them and files generated from those designs
Schematic (.kicad_sch) for EoS CM4 BasePCB layout (.kicad_pcb) for EoS CM4 Base

Native KiCad files from commit 28ec996, for viewing under this board’s full licence. Keep the licence with any permitted copies. The GitHub folder includes the project settings and supporting files.

EoS CM4 Base files on GitHub All boards
Perspective render of the EoS CM5 Base from its KiCad 3D model: the footprints of the two 100-pin module connectors, the USB-A port and the 40-pin GPIO header along one edge
Perspective
Top side of the EoS CM5 Base, rendered from its KiCad 3D model
Top
Bottom side of the EoS CM5 Base, rendered from its KiCad 3D model
Bottom

Renders and animation © 2026 Kartikeydheer Srivastava. All rights reserved.

EoS CM5 Base

A carrier board for the Raspberry Pi Compute Module 5, with USB-C power, Gigabit Ethernet, a USB 2.0 host port, microSD and the 40-pin GPIO header.

Status: designed and checked in KiCad; not yet manufactured or bench-tested.

Main chip
Raspberry Pi Compute Module 5, on two 100-pin connectors
Size
90 × 80 mm
Layers
4 (signal, GND plane, 5 V plane, signal; 1.6 mm)

Checks, as recorded

ERC violations
0
DRC errors
0
Unconnected
0
Schematic parity
0
DRC warnings
6

The 6 warnings: Silkscreen of the USB-C, USB-A and RJ45 connectors past the board edge, where edge connectors belong.

From build-report.json and drc.json in the board's folder, KiCad 10.0.6, commit 28ec996.

Key features, what is not done yet, and third-party material

Key features

  • Two Amphenol 10164227-1001A1RLF 100-pin connectors: all 200 pads, the module's four M2.5 holes and every ground, power and GPIO net checked against Raspberry Pi's CM5 data at KiCad's 1 nm resolution
  • USB-C power in and USB 2.0 device for rpiboot flashing and gadget mode, with USBLC6-2SC6 ESD protection
  • Gigabit Ethernet through a TRXCOM TRJG0926HENL MagJack, with TPD4EUSB30 ESD protection
  • USB 2.0 host on a USB-A port, its 5 V switched by a TPS2051C
  • microSD for CM5 Lite, powered through an RT9742GGJ5 switch
  • Standard 40-pin Raspberry Pi GPIO header at 3.3 V
  • Fan connector, RTC coin cell, power button, and nRPIBOOT and EEPROM write-protect jumpers
  • No copper on any layer under the module's PCB antenna: the 8 × 15 mm cut-out the CM5 datasheet calls ideal, where its Figure 4 puts the antenna, checked by a test

Not done yet

  • This board has not been manufactured, powered or tested on the bench.
  • No signal-integrity simulation: the Ethernet and USB 2.0 pairs are kept short, but their impedance has not been calculated or simulated.
  • HDMI, PCIe, USB 3.0 SuperSpeed and the camera and display (MIPI) interfaces are left off on purpose, because the generator cannot match or verify their differential pairs.
  • The MagJack footprint is this project's own and has no 3D model.

Third-party material, under its own licence

  • CM5 connector and mounting-hole positions and the CM5 pinout, from Raspberry Pi's CM5 datasheet and CM5 IO Board design files (facts only)
  • Schematic symbols in hardware/symbols, written by the repository's generator: MIT licence
  • Footprints, symbols and 3D models from KiCad's libraries: CC BY-SA 4.0, with the KiCad libraries' exception for designs that use them and files generated from those designs
Schematic (.kicad_sch) for EoS CM5 BasePCB layout (.kicad_pcb) for EoS CM5 Base

Native KiCad files from commit 28ec996, for viewing under this board’s full licence. Keep the licence with any permitted copies. The GitHub folder includes the project settings and supporting files.

EoS CM5 Base files on GitHub All boards
Perspective render of the EoS ATmega328P Board from its KiCad 3D model: the ATmega328P between the shield headers, a barrel jack and USB-C on the left edge
Perspective
Top side of the EoS ATmega328P Board, rendered from its KiCad 3D model
Top
Bottom side of the EoS ATmega328P Board, rendered from its KiCad 3D model
Bottom

Renders and animation © 2026 Kartikeydheer Srivastava. All rights reserved.

EoS ATmega328P Board

A 5 V, 16 MHz development board with the Uno R3 shield header layout and an original power and USB circuit.

Status: designed and checked in KiCad; not yet manufactured or bench-tested.

Main chip
Microchip ATmega328P-AU
Size
68.58 × 53.34 mm
Layers
2 (ground poured on both sides; 1.6 mm)

Checks, as recorded

ERC violations
0
DRC errors
0
Unconnected
0
Schematic parity
0
DRC warnings
4

The 4 warnings: Silkscreen outlines within the board-edge clearance at the edge connectors; see the board README for the recorded warnings.

From build-report.json and drc.json in the board's folder, KiCad 10.0.6, commit 28ec996.

Key features, what is not done yet, and third-party material

Key features

  • ATmega328P at 16 MHz, with ICSP programming and reset button
  • CH340C USB-UART with Ioff-rated isolation buffers and DTR auto-reset
  • USB-C or 7–12 V barrel input; AP63205 buck and TPS2116 power mux
  • Uno R3 shield headers, a 3.3 V output and power/user LEDs

Not done yet

  • This board has not been manufactured, powered or tested on the bench.
  • No firmware or bootloader has been run on this board; crystal margin and auto-reset timing remain unmeasured.
  • The 3.3 V header is an output. High-current shields need an external supply and must follow the README power limits.

Third-party material, under its own licence

  • Uno R3 header and mounting-hole dimensions from published dimension drawings and the Arduino product reference manual
  • Footprints, symbols and 3D models from KiCad's libraries: CC BY-SA 4.0, with the KiCad libraries' exception for designs that use them and files generated from those designs
Schematic (.kicad_sch) for EoS ATmega328P BoardPCB layout (.kicad_pcb) for EoS ATmega328P Board

Native KiCad files from commit 28ec996, for viewing under this board’s full licence. Keep the licence with any permitted copies. The GitHub folder includes the project settings and supporting files.

EoS ATmega328P Board files on GitHub All boards
Perspective render of the EoS MSP430G2 Board from its KiCad 3D model: a DIP-20 socket between the expansion headers, with USB-C and a debug header above it
Perspective
Top side of the EoS MSP430G2 Board, rendered from its KiCad 3D model
Top
Bottom side of the EoS MSP430G2 Board, rendered from its KiCad 3D model
Bottom

Renders and animation © 2026 Kartikeydheer Srivastava. All rights reserved.

EoS MSP430G2 Board

A socketed MSP430G2553 development board with 20-pin BoosterPack headers and an external Spy-Bi-Wire debug connection.

Status: designed and checked in KiCad; not yet manufactured or bench-tested.

Main chip
Texas Instruments MSP430G2553IN20
Size
56 × 80 mm
Layers
2 (ground poured on both sides; 1.6 mm)

Checks, as recorded

ERC violations
0
DRC errors
0
Unconnected
0
Schematic parity
0
DRC warnings
2

The 2 warnings: Silkscreen outlines within the board-edge clearance at the edge connectors; see the board README for the recorded warnings.

From build-report.json and drc.json in the board's folder, KiCad 10.0.6, commit 28ec996.

Key features, what is not done yet, and third-party material

Key features

  • Socketed DIP-20 MSP430G2553 and a 32.768 kHz crystal
  • 20-pin BoosterPack header layout
  • CP2102N USB-UART bridge and USB-C power input
  • MSP-FET connector for external Spy-Bi-Wire programming; no on-board eZ-FET

Not done yet

  • This board has not been manufactured, powered or tested on the bench.
  • No firmware, oscillator start-up or connected BoosterPack has been tested.
  • Programming needs an external Spy-Bi-Wire probe; security-fuse programming is not connected.

Third-party material, under its own licence

  • 20-pin BoosterPack header facts from TI’s published BoosterPack standard
  • Footprints, symbols and 3D models from KiCad's libraries: CC BY-SA 4.0, with the KiCad libraries' exception for designs that use them and files generated from those designs
Schematic (.kicad_sch) for EoS MSP430G2 BoardPCB layout (.kicad_pcb) for EoS MSP430G2 Board

Native KiCad files from commit 28ec996, for viewing under this board’s full licence. Keep the licence with any permitted copies. The GitHub folder includes the project settings and supporting files.

EoS MSP430G2 Board files on GitHub All boards
Perspective render of the EoS TM4C123 Board from its KiCad 3D model: the LQFP-64 MCU between four expansion-header rows, with two USB-C connectors
Perspective
Top side of the EoS TM4C123 Board, rendered from its KiCad 3D model
Top
Bottom side of the EoS TM4C123 Board, rendered from its KiCad 3D model
Bottom

Renders and animation © 2026 Kartikeydheer Srivastava. All rights reserved.

EoS TM4C123 Board

A Cortex-M4F development board with 40-pin BoosterPack headers, separate USB device and serial ports, and external SWD/JTAG.

Status: designed and checked in KiCad; not yet manufactured or bench-tested.

Main chip
Texas Instruments TM4C123GH6PM
Size
50.8 × 60 mm
Layers
2 (ground poured on both sides; 1.6 mm)

Checks, as recorded

ERC violations
0
DRC errors
0
Unconnected
0
Schematic parity
0
DRC warnings
4

The 4 warnings: Silkscreen outlines within the board-edge clearance at the edge connectors; see the board README for the recorded warnings.

From build-report.json and drc.json in the board's folder, KiCad 10.0.6, commit 28ec996.

Key features, what is not done yet, and third-party material

Key features

  • TM4C123GH6PM with 16 MHz and 32.768 kHz crystals
  • 40-pin BoosterPack expansion headers
  • MCU USB device port and a separate CP2102N USB-UART port
  • Cortex 10-pin SWD/JTAG header replaces the on-board debug interface

Not done yet

  • This board has not been manufactured, powered or tested on the bench.
  • The BoosterPack 5 V power path has a documented back-feed limitation; read the README before connecting an externally powered BoosterPack.
  • No hardware, firmware, USB signal integrity or thermal behaviour has been tested.

Third-party material, under its own licence

  • Schematic symbols in hardware/symbols (EoS_MCU.kicad_sym), written by the repository’s generator: MIT licence
  • 40-pin BoosterPack header positions and pin roles from TI’s published BoosterPack standards
  • Footprints, symbols and 3D models from KiCad's libraries: CC BY-SA 4.0, with the KiCad libraries' exception for designs that use them and files generated from those designs
Schematic (.kicad_sch) for EoS TM4C123 BoardPCB layout (.kicad_pcb) for EoS TM4C123 Board

Native KiCad files from commit 28ec996, for viewing under this board’s full licence. Keep the licence with any permitted copies. The GitHub folder includes the project settings and supporting files.

EoS TM4C123 Board files on GitHub All boards
Perspective render of the EoS KL25 Board from its KiCad 3D model: the LQFP-80 MCU and accelerometer inside the shield headers, beside two USB-C connectors
Perspective
Top side of the EoS KL25 Board, rendered from its KiCad 3D model
Top
Bottom side of the EoS KL25 Board, rendered from its KiCad 3D model
Bottom

Renders and animation © 2026 Kartikeydheer Srivastava. All rights reserved.

EoS KL25 Board

A 3.3 V Cortex-M0+ board with Uno R3 shield headers, a USB device port and an accelerometer.

Status: designed and checked in KiCad; not yet manufactured or bench-tested.

Main chip
NXP MKL25Z128VLK4
Size
68.58 × 53.34 mm
Layers
2 (ground poured on both sides; 1.6 mm)

Checks, as recorded

ERC violations
0
DRC errors
0
Unconnected
0
Schematic parity
0
DRC warnings
4

The 4 warnings: Silkscreen outlines within the board-edge clearance at the edge connectors; see the board README for the recorded warnings.

From build-report.json and drc.json in the board's folder, KiCad 10.0.6, commit 28ec996.

Key features, what is not done yet, and third-party material

Key features

  • Kinetis KL25Z with an 8 MHz crystal
  • MCU USB device port plus a CP2102N USB-UART bridge
  • LIS2HH12 accelerometer, RGB LED and reset button
  • Uno R3 header layout and Cortex 10-pin SWD header replacing OpenSDA

Not done yet

  • This board has not been manufactured, powered or tested on the bench.
  • Use only 3.3 V shields or shields that follow IOREF; 5 V logic can damage the MCU.
  • No touch slider or 7–12 V input; VIN is unconnected. No firmware or shield compatibility has been tested.

Third-party material, under its own licence

  • Uno R3 header and mounting-hole dimensions from published dimension drawings and the Arduino product reference manual
  • Footprints, symbols and 3D models from KiCad's libraries: CC BY-SA 4.0, with the KiCad libraries' exception for designs that use them and files generated from those designs
Schematic (.kicad_sch) for EoS KL25 BoardPCB layout (.kicad_pcb) for EoS KL25 Board

Native KiCad files from commit 28ec996, for viewing under this board’s full licence. Keep the licence with any permitted copies. The GitHub folder includes the project settings and supporting files.

EoS KL25 Board files on GitHub All boards
Perspective render of the EoS STM32 64 from its KiCad 3D model: two long morpho headers around the MCU and shield headers, with two USB-C ports
Perspective
Top side of the EoS STM32 64, rendered from its KiCad 3D model
Top
Bottom side of the EoS STM32 64, rendered from its KiCad 3D model
Bottom

Renders and animation © 2026 Kartikeydheer Srivastava. All rights reserved.

EoS STM32 64

A 3.3 V Cortex-M4F board in the Nucleo-64 format, with morpho and Uno headers and an external debug connection.

Status: designed and checked in KiCad; not yet manufactured or bench-tested.

Main chip
STMicroelectronics STM32F411RE
Size
70 × 82.5 mm
Layers
2 (ground poured on both sides; 1.6 mm)

Checks, as recorded

ERC violations
0
DRC errors
0
Unconnected
0
Schematic parity
0
DRC warnings
4

The 4 warnings: Silkscreen outlines within the board-edge clearance at the edge connectors; see the board README for the recorded warnings.

From build-report.json and drc.json in the board's folder, KiCad 10.0.6, commit 28ec996.

Key features, what is not done yet, and third-party material

Key features

  • STM32F411RE with 8 MHz and 32.768 kHz crystals
  • Uno V3 and two 2×19 morpho headers
  • CP2102N USART2 console and a separate MCU USB port for ROM DFU
  • Cortex Debug header replaces ST-LINK; USB and 7–12 V buck power paths

Not done yet

  • This board has not been manufactured, powered or tested on the bench.
  • The console UART is not the F411 ROM bootloader UART; use USB DFU or an external probe.
  • No USB host power switch. No firmware, oscillator or shield fit has been bench-tested.

Third-party material, under its own licence

  • Nucleo-64 dimensions and header pin assignments from ST’s published UM1724 user manual
  • Footprints, symbols and 3D models from KiCad's libraries: CC BY-SA 4.0, with the KiCad libraries' exception for designs that use them and files generated from those designs
Schematic (.kicad_sch) for EoS STM32 64PCB layout (.kicad_pcb) for EoS STM32 64

Native KiCad files from commit 28ec996, for viewing under this board’s full licence. Keep the licence with any permitted copies. The GitHub folder includes the project settings and supporting files.

EoS STM32 64 files on GitHub All boards
Perspective render of the EoS LPC55S69 Board from its KiCad 3D model: the exposed-pad HLQFP-100 MCU inside the shield headers, with two USB-C ports
Perspective
Top side of the EoS LPC55S69 Board, rendered from its KiCad 3D model
Top
Bottom side of the EoS LPC55S69 Board, rendered from its KiCad 3D model
Bottom

Renders and animation © 2026 Kartikeydheer Srivastava. All rights reserved.

EoS LPC55S69 Board

A dual Cortex-M33 board with Uno R3 shield headers, full-speed USB, a serial bridge and external SWD.

Status: designed and checked in KiCad; not yet manufactured or bench-tested.

Main chip
NXP LPC55S69JBD100
Size
68.58 × 53.34 mm
Layers
4 (signal, GND plane, 3.3 V plane, signal; 1.6 mm)

Checks, as recorded

ERC violations
0
DRC errors
0
Unconnected
0
Schematic parity
0
DRC warnings
4

The 4 warnings: Silkscreen outlines within the board-edge clearance at the edge connectors; see the board README for the recorded warnings.

From build-report.json and drc.json in the board's folder, KiCad 10.0.6, commit 28ec996.

Key features, what is not done yet, and third-party material

Key features

  • LPC55S69 with 16 MHz and 32.768 kHz crystals
  • Four layers with internal GND and 3.3 V planes
  • USB0 full-speed device and CP2102N USB-UART on separate ports
  • TPS2116 power mux, TPS7A91 regulator and external SWD header replacing LPC-Link2

Not done yet

  • This board has not been manufactured, powered or tested on the bench.
  • USB1 high speed, audio codec, microSD and extra expansion connectors are omitted.
  • Use 3.3 V shield logic. AREF, VIN and the Uno ICSP header are not connected or fitted; I2C is separate from A4/A5.
  • No firmware, USB signal integrity or hardware performance has been tested.

Third-party material, under its own licence

  • Schematic symbols in hardware/symbols (EoS_MCU.kicad_sym), written by the repository’s generator: MIT licence
  • Uno R3 header and mounting-hole dimensions from published dimension drawings and the Arduino product reference manual
  • Footprints, symbols and 3D models from KiCad's libraries: CC BY-SA 4.0, with the KiCad libraries' exception for designs that use them and files generated from those designs
Schematic (.kicad_sch) for EoS LPC55S69 BoardPCB layout (.kicad_pcb) for EoS LPC55S69 Board

Native KiCad files from commit 28ec996, for viewing under this board’s full licence. Keep the licence with any permitted copies. The GitHub folder includes the project settings and supporting files.

EoS LPC55S69 Board files on GitHub All boards
Perspective render of the EoS KE16Z Board from its KiCad 3D model: the LQFP-48 MCU between the shield headers, with USB-C, buttons and an RGB LED
Perspective
Top side of the EoS KE16Z Board, rendered from its KiCad 3D model
Top
Bottom side of the EoS KE16Z Board, rendered from its KiCad 3D model
Bottom

Renders and animation © 2026 Kartikeydheer Srivastava. All rights reserved.

EoS KE16Z Board

A 3.3 V Kinetis KE16Z board with Uno R3 shield headers, USB serial and CAN-controller pins for an external transceiver.

Status: designed and checked in KiCad; not yet manufactured or bench-tested.

Main chip
NXP MKE16Z64VLF4
Size
68.58 × 53.34 mm
Layers
2 (ground poured on both sides; 1.6 mm)

Checks, as recorded

ERC violations
0
DRC errors
0
Unconnected
0
Schematic parity
0
DRC warnings
2

The 2 warnings: Silkscreen outlines within the board-edge clearance at the edge connectors; see the board README for the recorded warnings.

From build-report.json and drc.json in the board's folder, KiCad 10.0.6, commit 28ec996.

Key features, what is not done yet, and third-party material

Key features

  • 48 MHz Cortex-M0+ with 64 KB flash, 8 KB SRAM and an 8 MHz crystal
  • CP2102N on LPUART1 and USB-C power
  • RGB LED, reset and two user buttons
  • External SWD replaces OpenSDA; MSCAN pins reach a separate header

Not done yet

  • This board has not been manufactured, powered or tested on the bench.
  • Use 3.3 V shield logic; never feed the 3V3 or IOREF outputs.
  • No CAN transceiver, touch electrodes, thermistor or 7–12 V input. VIN is unconnected.
  • No firmware, bus communication or thermal behaviour has been tested.

Third-party material, under its own licence

  • Uno R3 header and mounting-hole dimensions from published dimension drawings and the Arduino product reference manual
  • Footprints, symbols and 3D models from KiCad's libraries: CC BY-SA 4.0, with the KiCad libraries' exception for designs that use them and files generated from those designs
Schematic (.kicad_sch) for EoS KE16Z BoardPCB layout (.kicad_pcb) for EoS KE16Z Board

Native KiCad files from commit 28ec996, for viewing under this board’s full licence. Keep the licence with any permitted copies. The GitHub folder includes the project settings and supporting files.

EoS KE16Z Board files on GitHub All boards
Perspective render of the EoS RA2E1 Board from its KiCad 3D model: the LQFP-64 MCU between the shield headers, with Pmod connectors and a USB-C port
Perspective
Top side of the EoS RA2E1 Board, rendered from its KiCad 3D model
Top
Bottom side of the EoS RA2E1 Board, rendered from its KiCad 3D model
Bottom

Renders and animation © 2026 Kartikeydheer Srivastava. All rights reserved.

EoS RA2E1 Board

A Cortex-M23 board with Uno R3 shield headers, two Pmod connectors and a USB serial interface on the boot-programming UART.

Status: designed and checked in KiCad; not yet manufactured or bench-tested.

Main chip
Renesas R7FA2E1A92DFM
Size
68.58 × 53.34 mm
Layers
2 (ground poured on both sides; 1.6 mm)

Checks, as recorded

ERC violations
0
DRC errors
0
Unconnected
0
Schematic parity
0
DRC warnings
2

The 2 warnings: Silkscreen outlines within the board-edge clearance at the edge connectors; see the board README for the recorded warnings.

From build-report.json and drc.json in the board's folder, KiCad 10.0.6, commit 28ec996.

Key features, what is not done yet, and third-party material

Key features

  • 48 MHz RA2E1 with 128 KB code flash and 16 KB SRAM
  • CP2102N on SCI9 for console and serial boot programming with the MD jumper
  • Two Pmod headers and Uno R3 shield header layout
  • Cortex 10-pin SWD replaces J-Link OB; TPS7A91 3.3 V supply and 32.768 kHz crystal

Not done yet

  • This board has not been manufactured, powered or tested on the bench.
  • Use 3.3 V shield logic; AREF and VIN are unconnected and I2C is separate from A4/A5.
  • No touch electrode, main crystal or Uno ICSP header. No firmware, boot programming or connected module has been tested.

Third-party material, under its own licence

  • Schematic symbols in hardware/symbols (EoS_MCU.kicad_sym), written by the repository’s generator: MIT licence
  • Uno R3 header dimensions from published drawings; Pmod facts from Digilent’s Pmod Interface Specification
  • Footprints, symbols and 3D models from KiCad's libraries: CC BY-SA 4.0, with the KiCad libraries' exception for designs that use them and files generated from those designs
Schematic (.kicad_sch) for EoS RA2E1 BoardPCB layout (.kicad_pcb) for EoS RA2E1 Board

Native KiCad files from commit 28ec996, for viewing under this board’s full licence. Keep the licence with any permitted copies. The GitHub folder includes the project settings and supporting files.

EoS RA2E1 Board files on GitHub All boards

Licensing, partnerships and evaluation

Write to Kartikeydheer Srivastava at kartikeydheer@gmail.com. Each button opens an email with the subject filled in.

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Board files in eCAD pull request #60